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TC9462F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9462F
Digital Servo Single Chip Processor
The TC9462F is a single chip processor which incorporates the following function: synchronous separation protection and interpolation, EFM demodulation, Error correction, microcontroller interface, digital equalizer for use in servo LSI and servo control circuit. In addition, the TC9462F incorporates a 1 bit DA converter. In combination with the head amplifier TA2109F, TA2153FN for digital servo, the TC9462F allow simplified, adjustment-free structuring of CD player system.
Features
* * * * * * * * * * * * * * * * * * * * * * * * * * * * Capable of decode the text data. Built in EFM demodulation circuit, subcode demodulation circuit. Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical format. The TC9462F respond to variable playback system. Jitter absorbing capacity of 6 frames. Built in 16 KB RAM. Built in digital out circuit. Built in L/R independent digital attenuator. Audio output responds to bilingual function. Reed timing free subcode Q data and capable of synchronous output with audio data. Built in data slicer and analog PLL (free-adjustment VCO). Capable of automatic adjustment function of focus servo and tracking servo, for loop gain, offset and balance. Built in RF gain automatic adjustment circuit. Built in digital equalizer for phase compensation. Built in RAM for digital equalizer for coefficient, and capable of variable pickup. Built in focus, tracking servo control circuit. Search control corresponds to every mode and can realize high speed and stable search. Lens-kick are using speed controlled form. Built in AFC circuit and APC circuit for CLV servo of disc motor. Built in anti-defect and anti-shock circuit. Built in 8 times oversampling digital filter and 1 bit DA converter. Built in analog filter for 1 bit DA converter. Built in zero data detect output circuit. The TC9462F capable of 4 times speed operation. Built in microcontroller interface circuit. CMOS silicon structure and high speed, low power consumption. 100 pin flat package. Weight: 1.6 g (typ.) Sync pattern detection, sync signal protection and synchronization can be made correctly.
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TC9462F
Block Diagram (top view)
VCOREF PVREF
VCOF
SBAD
RFRP
RFCT
SLCO
AVDD
LPFO 32
TSIN
RFZI
FOO
TEZI
TRO
TEI
50
49
48
47
46
45
44
43
FEI
42
41
40
39
38
37
36
AVSS
RFI
35
34
33
31
RFGC 51 TEBC 52 FMO 53 D/A FVO 54 DMO 55 A/D 2VREF 56 PWM SEL 57 FLGA 58 FLGB 59 CLV servo status FLGC 60 FLGD 61 control Servo VDD 62 VSS 63 IO0 64 IO1 65 IO2 66 IO3 67 16 KRAM Digital out
DMOUT 68 CKSE 69 DACT 70
LPFN
VREF
30 TMAX 29 TMAXS 28 PDO 27 ZDET Data slicer PLL TMAX VCO 26 HSSW 25 P2VREF 24 TESIO0 23 VDD 22 MONIT Automatic adjustment circuit Digital equalizer 21 COFS 20 SPDA 19 SPCK 18 SBSY Synchronous guarantee EFM decode ROM RAM Sub code decoder 17 SFSY 16 DATA 15 VSS 14 VDD Address circuit 13 CLCK 12 SBOK 11 IPF 10 MBOV 9 DOUT 8 AOUT Correction circuit 7 BCK Audio out circuit 6 VSS 5 LRCK 4 EMPH 3 UHSO 2 HSO 1 TEST0
TESIO1 72 VSS 73 PXI 74 PXO 75 VDD 76 XVSS 77 LPF XI 78 XO 79 XVDD 80
1 bit DAC
Clock generator
TESIN 71
81 DVSR
82 RO
83 DVDD
84 DVR
85 LO
86 DVSL
87 TEST1
88 TEST2
89 TEST3
90 BUS0
91 BUS1
Micon interface 92 BUS2 93 BUS3
94 VDD
95 VSS
96 BUCK
97 CCE
98 TEST4
99 TSMOD
100
2
RST
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TC9462F
Pin Function
Pin No. 1 Symbol TEST0 I/O I Functional Description Test mode terminal. Normally, keep at open. Playback speed mode flag output terminal. 2
HSO
Remarks With pull-up resistor.
O
UHSO
HSO
Playback Speed Normal 2 times 4 times 3/4 3/4
H H L 3
UHSO
H L H L
O
L
4
EMPH
O
Subcode Q data emphasis flag output terminal. Emphasis ON at "H" level and OFF at "L" level. The output polarity can invert by command. Channel clock output terminal. (44.1 kHz) L-ch at "L" level and R-ch at "H" level. The output polarity can invert by command. Digital GND terminal. Bit clock output terminal. (1.4112 MHz) Audio data output terminal. Digital data output terminal. Buffer memory over signal output terminal. Over at "H" level. Correction flag output terminal. At "H" level, AOUT output is made to correction impossibility by C2 correction processing. Subcode Q data CRCC check adjusting result output terminal. The adjusting result is OK at "H" level. Subcode P~W data readout clock input/output terminal. This terminal can select by command bit. Digital power supply voltage terminal. Digital GND terminal. Subcode P~W data output terminal. Play-back frame sync signal output terminal. Subcode block sync signal output terminal. Processor status signal readout clock output terminal. Processor status signal output terminal. Correction frame clock output terminal. (7.35 kHz) Internal signal (DSP internal flag and PLL clock) output terminal. Selected by command. This terminal output the text data with serial by command. Digital power supply voltage terminal. Test input/output terminal. Normally, keep at "L" level. The terminal that inputted the clock for read of text data by command. PLL double reference voltage supply terminal. This terminal is used to output PVREF or HiZ by command. 1 bit DA converter zero detect flag output terminal. Phase difference signal output terminal of EFM signal and PLCK signal. 2-state output. (PVREF, HiZ) Schmitt input
3/4
5 6 7 8 9 10
LRCK VSS BCK AOUT DOUT MBOV
O 3/4 O O O O
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
11
IPF
O
12 13 14 15 16 17 18 19 20 21
SBOK CLCK VDD VSS DATA SFSY SBSY SPCK SPDA COFS
O I/O 3/4 3/4 O O O O O O
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
22 23 24 25 26 27 28
MONIT VDD TESIO0 P2VREF HSSW ZDET PDO
O 3/4 I 3/4 O O O
3/4 3-state output. (P2VREF, PVREF, VSS)
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Pin No. 29 Symbol TMAXS I/O O Functional Description TMAX detection result output terminal. Selected by command bit (TMPS). TMAX detection result output terminal. Selected by command bit (TMPS). TMAX Detection 30 TMAX O Longer than fixed freq. Shorter than fixed freq. Within the fixed freq. TMAX Output "P2VREF" "VSS" "HiZ" 3-state output. (P2VREF, HiZ, VSS) Remarks 3-state output. (P2VREF, PVREF, VSS)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
LPFN LPFO PVREF VCOREF VCOF AVSS SLCO RFI AVDD RFCT RFZI RFRP FEI SBAD TSIN TEI TEZI FOO TRO VREF RFGC TEBC FMO FVO DMO 2VREF SEL
I O 3/4 I O 3/4 O I 3/4 I I I I I I I I O O 3/4 O O O O O 3/4 O
LPF amplifier inverting input terminal for PLL. LPF amplifier output terminal for PLL. PLL reference voltage supply terminal. VCO center frequency reference level terminal. Normally, keep at "PVREF" level. VCO filter terminal. Analog GND terminal. Data slice level output terminal. RF signal input terminal. Analog power supply voltage terminal. RFRP signal center level input terminal. RFRP zero cross input terminal. RF ripple signal input terminal. Focus error signal input terminal. Sub-beam adder signal input terminal. Test input terminal. Normally, keep at "VREF" level. Tracking error signal input terminal. Take in at tracking servo on. Tracking error zero cross input terminal. Focus servo equalizer output terminal. Tracking servo equalizer output terminal. Analog reference voltage supply terminal. RF amplitude adjustment control signal output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) Tracking balance control signal output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) Feed equalizer output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) Speed error signal or feed search equalizer output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) Disc equalizer output terminal. (PWM carrier = 88.2 kHz for DSP, Synchronize to PXO) Analog double reference voltage supply terminal. APC circuit ON/OFF indication signal output terminal. At the laser on time, "HiZ" level at UHS = L and "H" level at UHS = H.
Analog input. Analog output. 3/4 3/4 Analog output. 3/4 Analog output. Analog input. (Zin: selected by command) 3/4 Analog input. (Zin: 50 kW) Analog input. Analog input. Analog input. Analog input. Analog input. Analog input. Analog input. (Zin: 10 kW) Analog output. (2VREF~AVSS) 3/4
3-state output. (2VREF, VREF, VSS)
3/4 3/4
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Pin No. Symbol I/O Functional Description External flag output terminal for internal signal. Can select signal from TEZC, FOON , FOK and RFZC by command. 59 FLGB O External flag output terminal for internal signal. Can select signal from DFCT , FOON , FMON and RFZC by command. 60 FLGC O External flag output terminal for internal signal. Can select signal from TRON , TRSR , FOK and SRCH by command. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 FLGD VDD VSS IO0 IO1 I/O IO2 IO3
DMOUT CKSE DACT
Remarks
58
FLGA
O
3/4
3/4
3/4
O 3/4 3/4
External flag output terminal for internal signal. Can select signal from TRON , DMON , HYS and SHC by command. Digital power supply voltage terminal. Digital GND terminal. General I/O terminal be changed over input port or output port by command. At the input port mode, it can readout a state of terminal (H/L) by read command. At the output port mode, it outputs (H/L/HiZ) by command.
3/4 3/4 3/4
3/4
I I I I I 3/4 I O 3/4 3/4 I O 3/4 3/4 O 3/4 3/4 O 3/4 I I I I/O I/O
"L" active, when this terminal is set "L", IO 0/1 and 2/3 output feed equalizer signal and disc equalizer signal of 2-state With pull-up resistor. PWM respectively. Normally, keep at open. DAC test mode terminal. Normally, keep at open. Test input terminal. Normally, keep at "L" level. Test input/output terminal. Normally, keep at "L" level. Digital GND terminal. Crystal oscillator connecting input terminal for DSP. Normally, keep at "L" level. Crystal oscillator connecting output terminal for DSP. Digital power supply voltage terminal. Oscillator GND terminal for system clock. Crystal oscillator connecting input terminal for system clock. Crystal oscillator connecting output terminal for system clock. Oscillator power supply voltage terminal for system clock. Analog GND terminal for DA converter. (R-ch) R channel data forward output terminal. Analog supply voltage terminal for DA converter. Reference voltage terminal for DA converter. L channel data forward output terminal. Analog GND terminal for DA converter. (L-ch) Test mode terminal. Normal, keep at open. Test mode terminal. Normal, keep at open. Test mode terminal. Normal, keep at open. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 With pull-up resistor. With pull-up resistor. With pull-up resistor. With pull-up resistor. With pull-up resistor. Analog input. 3/4 3/4 3/4
TESIN TESIO1 VSS PXI PXO VDD XVSS XI XO XVDD DVSR RO DVDD DVR LO DVSL TEST1 TEST2 TEST3 BUS0 BUS1 BUS2 BUS3 VDD
Micon interface data input/output terminal. I/O I/O 3/4 Digital power supply voltage terminal.
Schmitt input. With pull-up resistor.
3/4
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Pin No. 95 96 97 98 99 100 Symbol VSS BUCK
CCE
I/O I I I I I
Functional Description Digital GND terminal. Micon interface clock input terminal. Command and data sending/receiving chip enable signal input terminal. The bus line becomes active at "L" level. Test mode terminal. Normal, keep at open. Local test mode selection terminal. Reset signal input terminal. Reset at "L" level.
Remarks 3/4 Schmitt input. Schmitt input. With pull-up resistor. With pull-up resistor. With pull-up resistor.
TEST4
TSMOD RST
Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VIN PD Topr Tstg Rating -0.3~6.0 -0.3~VDD + 0.3 1420 -40~85 -55~150 Unit V V mW C C
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TC9462F
Electrical Characteristics
(unless otherwise specified, VDD = AVDD = DVDD = XVDD = 5 V, 2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V, Ta = 25C)
DC Characteristics
Characteristics Assured supply voltage Symbol VDD Test Circuit 3/4 Test Condition Ta = -40~85C Normal speed 4 times speed XI = 16.9344 MHz Min 4.5 45 50 3.5 3/4 3/4 -1.0 3/4 -0.1 3/4 2.0 3/4 2.0 following (3) -1.4 0.6 following (4) 3/4 2.0 3/4 25.0 1.0 Typ. 5.0 50 55 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50.0 2.0 Max 5.5 60 mA 65 3/4 1.5 1.0 3/4 0.1 3/4 -1.0 3/4 -1.0 3/4 -0.6 1.4 -1.0 3/4 500 75.0 3.0 W kW MW mA mA Unit V
Assured supply current
IDD
3/4
"H" Level Input voltage "L" Level "H" Level Input current "L" Level Tri-state leak current "H" Level "L" Level "H" Level "L" Level "H" Level Output current "L" Level "H" Level "L" Level "H" Level "L" Level VREF output ON resistor Pull-up resistor Osc. Amp. feedback resistor
VIH VIL IIH IIL ITLH ITLL IOH (1) IOL (1) IOH (2) IOL (2) IOH (3) IOL (3) IOH (4) IOL (4) RON RUP RN
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
CMOS input terminal (except analog input) VIH = 5 V VIL = 0 V VIH = 5 V VIL = 0 V CMOS Input Terminal (except analog input) following (1)
V
mA
VOH = 4.6 V following (1) (except TMAXS, VOL = 0.4 V TMAX) VOH = 4.6 V VOH = 0.4 V VOH = 4.6 V VOL = 0.4 V VOH = 3.8 V VOL = 0.4 V following (2)
following (4) (except TMAXS, TMAX) following (5) between XI-XO and PXI-PXO terminal
Terminal Name
HSO , UHSO , EMPH, DOUT, MBOV, IPF, SBOK, CLCK, TESIO1 DATA, SFSY, SBSY, SPCK, MONIT, TESIO0, TMAXS, TMAX, SEL FLGA, FLGB, FLGC, FLGD, IO0, IO1, IO2, IO3
(1) Terminal (2) Terminal (3) Terminal (4) Terminal (5) Terminal
LRCK, BCK, AOUT, SPDA, COFS, ZDET BUS0~3 PDO, TMAXS, TMAX, RFGC, TEBC, FMO, FVO, DMO
DMOUT , CKSE , DACT , TSMOD, RST , TEST0~4
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AC Characteristics
1. Microcomputer Interface Timing
Characteristics
CCE "H" clock pulse width CCE status data access time
Symbol tCC tCS tSZ1 tCB tBLW tBLW
Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Test Condition 3/4
CCE falling reference CCE rising reference CCE falling reference
Min 120 0 0 0 120 240 120 3000 1500 800 60 20 0 0 0 0
Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Max 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Unit
Status data disable time
CCE , BUCK delay pulse width
Write, SRC mode QDRC mode Write, SRC mode QDRC mode (1) QDRC mode (2) QDRC mode (4) BUCK rising reference BUCK rising reference BUCK falling reference BUCK falling reference BUCK falling reference BUCK rising reference
BUCK "L" clock pulse width BUCK "H" clock pulse width (1) BUCK "H" clock pulse width (2) BUCK "H" clock pulse width (3) BUCK "H" clock pulse width (4) Write data set-up time Write data hold time PRTY data access time Data disable time Read data access time Data disable time
tBHW tBHW tBHW tBHW tWS tWH tBA tSZ2 tRD tSZ3
ns
(1)
Idle mode
CCE
tCC
BUCK
BUSi
BUSi (output)
ST tCS Idol mode tSZ1
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TC9462F
(2) Write command mode
tCC CCE tBLW tBHW BUCK tCB BUSi (input) tCS BUSi (output) ST Idol mode Write mode tWS tWH CM tSZ2 CL DM DL tBA PRTY tSZ3
(3)
BXXXXX, FXXXXX command at
tCC
CCE tBLW tBHW BUCK tCB BUSi (input) tCS BUSi (output) ST tWS tWH CM tSZ2 CL DM DL EM EL tBA tSZ3 PRTY
(4)
Read command mode
tCC
CCE tBLW tBHW BUCK tCB BUSi (input) tCS BUSi (output) ST Idol mode tWS tWH CM tSZ2 tRD tSZ3 RD0 Write mode tBA RDn PRTY tSZ3
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TC9462F
2. AOUT Terminal Output Data Timing
Characteristics Transfer time (1) "H" Level "L" Level Symbol tpLH tpHL Test Circuit 3/4 3/4 Test Condition BCK (R) AOUT Min 3/4 3/4 Typ. 3/4 3/4 Max 5 5 Unit ns
BCK tpHL tpLH AOUT
3. SPDA Output Timing
Characteristics Transfer time "H" Level "L" Level Symbol tpLH tpHL Test Circuit 3/4 3/4 Test Condition SPCK (R) SPDA Min 3/4 3/4 Typ. 3 3 Max 3/4 3/4 Unit ns
SPCK
SPDA tpHL tpLH
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4. DATA, CLCK Input/Output Timing
(1) CLCK input mode
Characteristics Clock pulse width Input set-up time Transfer time (1) Transfer time (2) "L" Level "L" Level "H" Level "H" Level "L" Level Symbol tHW tLW tSu tpHL1 tpLH2 tpHL2 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 tpHL2 tpLH2 CLCK input mode Test Condition Min 200 200 200 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 Max 3/4 3/4 3/4 5 20 20 ns Unit
tpHL1 SFSY/COFS tSU CLCK tHW
tLW
DATA
SUBP
SUBQ
(2)
CLCK output mode (tHW, tLW, tpLH3; 2 times speed = 1/2, 4 times speed = 1/4)
Characteristics Symbol tHW tLW tpHL1 tpLH2 tpHL2 tpLH3 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 tpHL2 tpLH2 CLCK output mode Test Condition Min 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 Max 1000 1000 5 20 20 900 ns Unit
Clock pulse width Transfer time (1) Transfer time (2)
"H" Level "L" Level "L" Level "H" Level "L" Level
Transfer time (3)
"H" Level
tpHL1 SFSY/COFS tpLH3 CLCK tHW
tLW
DATA
SUBP
SUBQ
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5. SBSY, SBOK Input/Output Control
Characteristics Transfer time (1) "H" Level "L" Level "H" Level Transfer time (2) "L" Level Symbol tpLH1 tpHL1 tpLH2 tpHL2 Test Circuit 3/4 3/4 3/4 3/4 SBSY Test Condition Min 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 Max 5 5 15 15 ns Unit
SBOK
SFSY/COFS
tpLH1 SBSY
tpHL1
SBOK
tpLH2 tpHL2
6. Output Terminal Timing
Characteristics Output rising time (1) Output falling time (1) Output rising time (2) Output falling time (2) Output rising time (3) Output falling time (3) Output falling time (4) Symbol tor1 tof1 tor2 tof2 tor3 tof3 tor4 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Terminal (4) Output rising time (4) tof4 3/4 Test Condition Terminal (1) Min 3/4 3/4 3/4 3/4 3/4 3/4 VREF (R) 2VREF VSS (R) VREF 2VREF (R) VREF VREF (R) VSS 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 20 15 20 15 20 15 20 10 15 10 ns Unit
Terminal (2)
Terminal (3)
Terminal Name (1) Terminal (2) Terminal (3) Terminal (4) Terminal AOUT, BCK, COFS, LRCK BUS0, BUS1, BUS2, BUS3, CLCK DATA, DOUT, EMPH, FLGA, FLGB, FLGC, FLGD, HSO , IO0, IO1, IO2 IO3, IPF, MONIT, MBOV, SBOK, SBSY, SEL, SFSY, SPCK, UHSO PDO, TMAXS, TMAX, RFGC, TEBC, FMO, DMO, FVO
VOH VOH/2 VSS tor tof
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Analog Circuit Characteristics
1. A/D Converter
Characteristics Resolution FE TE Sampling frequency SBAD RFRP Conversion input range Ex. VSS = 0 V, 2VREF = 4.2 V XI = 16.9344 MHz Test Condition 3/4 Min 3/4 3/4 3/4 3/4 3/4 0.15 2VREF Typ. 8 176.4 176.4 88.2 176.4 3/4 Max 3/4 3/4 3/4 3/4 3/4 0.85 2VREF Unit bit KHz KHz KHz KHz V
2. D/A Converter (focus, tracking equalizer output)
Characteristics Bit number Sampling frequency Output signal range Test Condition 3/4 3/4 3/4 Min 3/4 3/4 AVSS Typ. 5 2.8 3/4 Max 3/4 3/4 2VREF Unit bit MHz V
3. PLL Filter Amp.
Characteristics Input/output signal range Frequency characteristics Test Condition 3/4 -3 dB point, RNF = 15 kW Min VSS 2 Typ. 3/4 4 Max 2VREF 3/4 Unit V MHz
4. VCO (PLL)
Characteristics Center oscillation frequency Test Condition LPFO = VREF, VCOREF = VREF VCOREF = VREF, VCOGSL = "H" VCOREF = VREF, VCOGSL = "L" VREF reference Min 3/4 40 3/4 3/4 -0.5 Typ. 34.6 50 40 3/4 3/4 Max 3/4 3/4 % 3/4 1.0 3/4 V Unit MHz
Frequency variation range
VCOREF terminal input voltage range
upper limit lower limit
5. TEZI Signal Comparator
Characteristics Input range Input amplitude Hysteresis voltage Test Condition 3/4 3/4 VREF reference Min VSS 1.0 3/4 Typ. 3/4 3/4 100 Max 2VREF 3.5 3/4 Unit V Vp-p mV
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6. RFZI Signal Comparator
Characteristics Input range Input amplitude Hysteresis voltage Test Condition 3/4 3/4 VREF reference (no external register to RFCT terminal) Min VSS 1.0 3/4 Typ. 3/4 3/4 100 Max 2VREF 3.5 3/4 Unit V Vp-p mV
7. Data Slicer Circuit
Characteristics (comparator) Input amplitude Response time (R-2R DAC) Output conversion range Output impedance 3/4 3/4 1.58 3/4 3/4 2.5 2.59 3/4 V kW VREF reference RFI = 0.6 Vp-p, f = 700 kHz 3/4 30 1.2 60 2.0 90 Vp-p ns Test Condition Min Typ. Max Unit
8. PWM Converter Output (RFGC, TEBC, FMO, FVO, DMO)
Characteristics PWM accuracy Sampling frequency Output signal range Test Condition 3/4 3/4 3/4 Min 3/4 3/4 AVSS Typ. 8 88.2 3/4 Max 3/4 3/4 2VREF Unit bit kHz V
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DAC Characteristics
Characteristics Total harmonic distortion + noise S/N ratio Dynamic range Symbol THD + N S/N DR Test Circuit 1 1 1 Test Condition 1 kHz sine wave, full scale input, PXI = "L" PXI = "L" 1 kHz sine wave, -60dB input conversion, PXI = "L" 1 kHz sine wave, full scale input, PXI = "L" 1 kHz sine wave, full scale input, PXI = "L" Min 3/4 90 85 3/4 1.12 Typ. -85 100 90 -90 1.20 Max -80 3/4 3/4 -85 1.28 Unit dB dB dB
Cross talk Analog output amplitude
CT DAC out
1 1
dB Vrms
Test Circuit 1: Application Circuit is Used.
TC9462F Application circuit
Lout Rout
20 kHz ideal LPF
Distortion meter
LPF: SHIBASOKU 725C (built-in filter) Distortion meter: SHIBASOKU 725C (corresponding)
Characteristics THD + N, CT S/N, DR
Distortion Filter Setting: A-wait OFF ON
A-WAIT: IEC-A (corresponding)
Application Circuit
TC9462F 5V XVDD 16.9344 MHz XI XO XVSS DVDD DVR LO PXI DVSL 100 mF 0.1 mF 270 W 3.3 mF 2200 pF L-ch Analog out 10 k9 DVSR RO 270 W 5V 3.3 mF 2200 pF R-ch Analog out 10 k9
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Package Dimensions
Weight: 1.6 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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